module dec1 ( input wire s0, input wire en_, output wire q0_, output wire q1_ ); assign q0_= !(!en_ & (!s0)); assign q1_= !(!en_ & ( s0)); endmodule // dec1 module dec2 ( input wire s0, input wire s1, input wire en_, output wire q0_, output wire q1_, output wire q2_, output wire q3_ ); assign q0_= !(!en_ & (!s1 & !s0)); assign q1_= !(!en_ & (!s1 & s0)); assign q2_= !(!en_ & ( s1 & !s0)); assign q3_= !(!en_ & ( s1 & s0)); endmodule // dec2 module dec3 ( input wire s0, input wire s1, input wire s2, input wire en_, output wire q0_, output wire q1_, output wire q2_, output wire q3_, output wire q4_, output wire q5_, output wire q6_, output wire q7_ ); assign q0_= !(!en_ & (!s2 & !s1 & !s0)); assign q1_= !(!en_ & (!s2 & !s1 & s0)); assign q2_= !(!en_ & (!s2 & s1 & !s0)); assign q3_= !(!en_ & (!s2 & s1 & s0)); assign q4_= !(!en_ & ( s2 & !s1 & !s0)); assign q5_= !(!en_ & ( s2 & !s1 & s0)); assign q6_= !(!en_ & ( s2 & s1 & !s0)); assign q7_= !(!en_ & ( s2 & s1 & s0)); endmodule // dec3 module dec4 ( input wire s0, input wire s1, input wire s2, input wire s3, input wire en_, output wire q0_, output wire q1_, output wire q2_, output wire q3_, output wire q4_, output wire q5_, output wire q6_, output wire q7_, output wire q8_, output wire q9_, output wire q10_, output wire q11_, output wire q12_, output wire q13_, output wire q14_, output wire q15_ ); assign q0_ = !(!en_ & (!s3 & !s2 & !s1 & !s0)); assign q1_ = !(!en_ & (!s3 & !s2 & !s1 & s0)); assign q2_ = !(!en_ & (!s3 & !s2 & s1 & !s0)); assign q3_ = !(!en_ & (!s3 & !s2 & s1 & s0)); assign q4_ = !(!en_ & (!s3 & s2 & !s1 & !s0)); assign q5_ = !(!en_ & (!s3 & s2 & !s1 & s0)); assign q6_ = !(!en_ & (!s3 & s2 & s1 & !s0)); assign q7_ = !(!en_ & (!s3 & s2 & s1 & s0)); assign q8_ = !(!en_ & ( s3 & !s2 & !s1 & !s0)); assign q9_ = !(!en_ & ( s3 & !s2 & !s1 & s0)); assign q10_= !(!en_ & ( s3 & !s2 & s1 & !s0)); assign q11_= !(!en_ & ( s3 & !s2 & s1 & s0)); assign q12_= !(!en_ & ( s3 & s2 & !s1 & !s0)); assign q13_= !(!en_ & ( s3 & s2 & !s1 & s0)); assign q14_= !(!en_ & ( s3 & s2 & s1 & !s0)); assign q15_= !(!en_ & ( s3 & s2 & s1 & s0)); endmodule // dec4