Parallel Architectures
Parallel Architectures is activity of the PARALLEL
TEMPUS project.
Available kind of materials:
- Document in HTML
format
- Document in (Gzipped)
Postscript
- Transparencies in
(Gzipped) Postscript
Overview
- Introduction MIMD
architectures
Document (12 pages Gzipped
Postscript 37k) by Péter Kacsuk
Transparencies (9 slides Gzipped
Postscript 22k, Zipped Winword
20k) by Zsolt
Németh
Abstract (HTML)
- Architectural concepts
- Problems of scalable computers
- Main design issues of scalable MIMD computers
- Introduction to IFP
architectures by Péter
Broczkó
Document (21 pages Gzippped Postscript
83k)
Transparencies (27 slides Gzipped Postscript 60k, Zipped WinWord 62k)
Abstract (HTML)
- Overview of IFP processors
- Constraints on parallel instruction execution
- The speed-up potential of functional parallelism
- Superscalar
architectures by Dezsô Sima
Document (Part I. of the document, 27 pages Gzipped Postscript 83k, Zipped WinWord 74k)
(Part II. of the document, 43 pages Gzipped Postscript 122k, Zipped WinWord 121k)
(Part III. of the document, 56 pages Gzipped Postscript 172k, Zipped WinWord 134k)
Transparencies (Zipped Winword 258k)
- Introduction
- Parallel decoding
- Superscalar instruction issue
- Shelving
- Register renaming
- Parallel execution
- Preserving the sequential consistency of instruction execution
- Preserving the sequential consistency of exception processing
- Implementation of superscalar CISC-processors using a superscalar
RISC core
- Case studies of superscalar processors
- Multi-threaded
architectures
Document (40 pages Gzipped Postscript
117k) by Péter
Kacsuk
Transparencies (38 slides Gzipped
Postscript 115k, Zipped
Winword) by Zsolt
Németh
Abstract (HTML)
- Introduction
- Computational models
- Neumann based multi-threaded architectures
- Dataflow architectures
- Summary
- Shared memory
architectures
Document (105 pages Gzipped
Postscript 333k) by Péter Kacsuk
Transparencies (72 slides Zipped Winword 22k, Zipped Winword 129k, Zipped Winword 70k) by Etelka Kovács
- Introduction
- Dynamic interconnection networks
- Cache coherence
- Synchronization and event ordering in multiprocessors
- Uniform Memory Access (UMA) Machines
- Non-Uniform Memory Access (NUMA) Machines
- Cache-Coherent Non-Uniform Memory Access (CC-NUMA) Machines
- Cache-Only Memory Architectures (COMA) Machines
- Summary
- Distributed memory
architectures
Document (70 pages Gzipped
Postscript 208k) by Péter Kacsuk
Transparencies (72 slides Gzipped Postscript 184k, Zipped Winword 382k) by Gyula Fehér
- Introduction
- Direct interconnection networks
- Fine-grain systems
- Medium-grain systems
- Coarse-grain multicomputers
- Summary
- Case examples:
Literature
[DoA]
[TEMPUS]
[MODIFY]
[PARALLEL]
[DOWNLOAD]
[UPLOAD]
[SEARCH]
[FEEDBACK]